A diode may be switched from a conducting state (forward-bias) to a non-conducting (reverse-bias) state. The speed at which the switching can occur may be limited by the time it takes to remove or add electrical charge to/from the depletion region of the diode. The time may be based on two parameters: the lifetime of the carriers, τn and τp, and the capacitance of the junction area. In the switching process, excess minority carriers (holes in the n region and electrons in the p region) which exist under forward-bias have to “recombine away” through the depletion region. Moreover, a larger junction area allows for a larger current to flow, and the series resistance drops. Conventional fin-based diodes, formed by growing embedded silicon germanium (eSiGe) at the top of p+ fins, with the p+/n-well junction at the interface between the fin and the eSiGe, suffer from non-ideality and leakage, among other things. The junction can be optimized by making the entire fin of grown eSiGe. The optimized diode has low leakage current and an excellent ideality range, even at increased temperatures.
RF diodes have characteristics that make them particularly attractive in IC devices. For example, an RF diode has an increased depletion region width over a conventional diode, which leads to lowering of capacitance. In addition, for small signals at high frequencies the stored carriers within the intrinsic layer are not completely swept by the RF signal or recombined (due to a large Fin height region). At such frequencies there is no rectification or distortion, and the RF diode characteristic is that of a linear resistor, which introduces no distortion or rectification. The RF diode resistance is governed by the DC bias applied. In this way it is possible to use the device as an effective RF switch or variable resistor for an attenuator producing far less distortion than ordinary PN junction diodes. However, RF diodes implemented in fin-type devices not only need to meet performance characteristics such as leakage current, ideality, and breakdown voltage, but also need to prevent increases in parasitic resistance or capacitance. With scaling down of IC devices, the fin width is reduced, thereby reducing the junction area in reverse biasing mode and increasing parasitic capacitance and resistance.
Therefore, a need exists for methodology enabling fabrications of smaller fin-based diodes with low leakage current and ideality as well as low capacitance and carrier storage and increased current, and the resulting devices.